A compact Raspberry Pi Compute Module 5 carrier that fits the Sony VAIO P chassis: onboard 2230 NVMe, USB-C power and host ports, a display FFC toward the Koyomi LVDS board, and a long series of fit, height, and manufacturability revisions.
Left to right in date order, one lane per concurrent line. A ring marks a revision that forked more than once; a diamond
marks one restarted from an earlier baseline while re-applying a later floorplan. Click a node to jump to its revision.
67 revisions carry a compressed glTF model.
With this many, each loads on request; up to six stay live at once.
Contact sheet
68 boards at a glance.
Every revision in lineage order, left to right and wrapping. A tile that does not continue from the one before it shows
where it forked from. True scale sizes each board by its real outline, so you can watch the carrier grow, shrink and turn.
The untouched open-source seed: the smallest routed, manufactured CM5 carrier with same-edge USB-C ports and onboard M.2 2230 NVMe. Kept in the tree so every later change can be diffed against its source.
Paid prototype order · placement stop A line · 78 × 52 mmordered
The released prototype with corrected USB-C orientation and stocked assembly connectors. CM5 sockets sit on the back opposite the SSD, which drives the 9.77 mm populated envelope, the tallest of any revision. The order carries a documented stop on the submitted placement file.
The outline grows to 91.69 × 52 mm so the CM5 and the 2230 SSD sit adjacent on the bottom face instead of opposing each other. Global height barely moves because the gain is local, not global. Fabrication gated on fine-via acceptance and on the chassis cavity being measured.
The big height win: 7.42 mm populated, 2.36 mm below A2. Both USB-C receptacles, the M.2 3.3 V regulator island and the bulk capacitor move to the back, leaving only 0.95 mm of top-side parts. The full DSI/CSI circuit stays as an optional unpopulated footprint.
Incremental fork of A3.2 adding USB 2.0 and microSD on optional horizontal FFC landings at the right edge. Because the new I/O is unpopulated by default, the populated height stays at A3.2's figure.
Corrects the USB role assignment: the right-side cable is the internal keyboard link and only needs USB 2.0, so USB 3 moves to the left, user-facing edge. Both Type-C positions standardise on one Molex receptacle with a TI HD3SS3220 as CC controller and SuperSpeed mux.
Sourcing fork of A3.4 that swaps the microSD FFC connector for a part the assembler actually stocks. Same footprint count; its value is the connector comparison.
Closes the four findings raised against A3.4: an active-low VBUS switch matching the active-low attach signal, separate switched rails for the user port and keyboard, a corrected port strap, and every SuperSpeed pair re-routed to under 0.12 mm intra-pair skew with symmetric via counts.
Sources the Type-C controller's 3.3 V rail, previously an unpowered net, and adds a fail-safe enable network so a missing 3.3 V domain cannot leave the controller enabled from 5 V alone. Also corrects the symbol's pin types, restoring ERC coverage on the most complex IC on the board.
Adds unpopulated debug UART holes. The highest footprint count of the A3 line, and the branch point for both the JLC upload chain and the daughter-card architecture.
The largest structural change in the series. Both USB-C receptacles, the SuperSpeed mux, the ESD parts and every strap move to a separate left-hand port card reachable over a 31-way 0.3 mm FFC. Footprint count falls from 75 to 57 and only four host-side SuperSpeed signals cross the cable.
Placement study · routing gate fails A3 line · 91.69 × 52 mm
Demonstrates the straight top-edge cable path and replaces the generic connector proxy with Hirose's exact STEP model. Explicitly a placement study: the routing gate fails and no waiver was created.
Live quote · sockets short A3 line · 91.69 × 52 mm
Closes A3.10's routing and is the first revision with a real assembler quote. The quote stalled at component matching because both CM5 socket rows were short.
Rigid four-layer port card carrying both USB-C receptacles, the SuperSpeed mux and the ESD parts, reachable from the A3.9 carrier over a 31-way FFC. Orphaned when B2.6 brought the receptacles back onto the carrier.
Flips the NVMe orientation and closes the resulting routing. Same outline, stack and footprint count as A3.10.1; the head of the merged daughter-card line.
Bill-of-materials closure on the A3.8.1 artwork so every fitted part resolves to a stocked assembler part. Only its render set is kept on the main branch.
Evaluates a stocked SHOU HAN 24-pin USB-C receptacle at both Type-C positions using the supplier's exact footprint. Kept as a deliberately failing footprint-evaluation snapshot.
Replaces the 31-way signal FPC plus the four-way power harness with one 20-contact I-PEX CABLINE-CA-II interface to the port card, keeping the flipped M.2 socket. An engineering work in progress that never merged.
Applies the safe parts of the cost-reduction study to A3.13 and corrects an off-board PD stage and a mounting-hole crossing found visually. Supersedes A3.13's unmerged pull request.
Completes a native fanout for the stocked QCHT receptacle at both USB-C positions. The connector was later rejected; B1 explicitly excludes it and the upload chain kept the Molex artwork.
The upload snapshot: PCB and schematic hashes match the verified A3.8.1/A3.8.2 Molex USB-C artwork. Both the B1 assembly experiment and the VBUS correction chain fork from here.
Preserves the A3.8.5 placement, routing and stack and changes only two current-limit resistors, lifting the user USB-C VBUS switch above the controller's default SuperSpeed advertisement and restoring the keyboard rail's limit.
Connector and fabrication correction — the fabricated board
Fabricated · 5 boards received A3 line · 91.69 × 52 mmfabricatedbring-up
The revision that actually went to the board house: the A3.8.6 electrical state with the right-edge USB/keyboard FFC rotated to face the board edge and the manufacturing handoff corrected. Five boards came back on 2026-08-18. First bench bring-up booted a CM5 from eMMC through the carrier's USB-C power path; the physical return logged a backward SD FFC and an NVMe growing across the board, both corrected in the B2 line. Its display FFC must not be connected to an LCD.
An immutable major-revision fork of the A3.8.5 upload snapshot aimed at bottom-only production assembly while keeping both CM5 sockets, the M.2 interface, the two Molex USB-C ports and the fitted breakouts. The last revision to carry the 91.69 × 52 mm landscape outline.
Architecture fork · unrouted B2 line · compact portrait
Fresh architecture fork of A3.8.6: the outline goes portrait at exactly the OEM logic board's 65.4 × 74.8 mm footprint, both carrier-mounted USB-C receptacles leave the board, and their interface collapses into one 40-position shielded FFC toward a left-hand companion card. Deliberately unrouted.
LCD interconnect revision B2 line · compact portraitKoyomi contract
Fabrication-ready successor for the display link: the display FFC gains the repurposed panel-ID and insertion contacts that the Koyomi LCD R2.6 contract verifies against.
Interconnect contract match B2 line · compact portrait
The USB 2.0 breakout connector becomes the exact JST GH part with the pin order that mates the I/O breakout board straight through, so no custom harness is needed.
Moves the cable interfaces to their requested chassis edges and reverses the SD FFC by 180°, the correction the A3.8.7 physical return later proved necessary. A routing-in-progress checkpoint.
Removes 15 mm from the short edge by rotating the CM5 arrangement; a small top-edge tab carries the full M.2 land pattern, giving a 50.4 × 80.4 mm bounding envelope.
Mechanical floorplan checkpoint B2 line · compact portrait
Mechanical checkpoint that rotates the 2230 NVMe by 90°, deletes the left-hand USB-C flex interface entirely and brings two direct Molex USB-C receptacles back onto the carrier's bottom edge, reversing the A3.9 off-board migration and orphaning the companion-card line.
Restores the complete USB 3/Type-C front end on the compact 50.4 × 75.5 mm outline. Errors-only DRC reports zero violations with six unconnected items and no exclusions; uses fine vias that must be quoted as a six-layer fine-hole board.
Interface and mechanical-placement checkpoint forked from B2.7 that adds one carrier battery connector on a local right-side wing between the USB 2.0 and microSD interfaces. The connector stays unpopulated until the charger and power path are settled.
Forks B2.7 intact and adds a full-size HDMI receptacle on a lower-right wing, CM5IO-style power and activity indicators, and a keyed active-low power-switch input. Fabrication blocked until the schematic and routing complete.
The short axis grows to a hard maximum of 52 mm while the CM5 sockets and the M.2 connector move to the top face and the edge HDMI receptacle becomes Mini HDMI. Adds the power-switch and boot/service landings that later revisions keep.
Mechanical decision · unrouted B2 line · compact portrait
Keeps the short dimension at 52 mm and extends the long one to 91.5 mm so every fitted part sits on the top side and the assembled bottom has no height governor. Provides a flush plated retention hole for a 2230 drive; longer drives overhang the rear edge. The all-top placement invalidates the B2.14.2 routes.
Model-only fork of B2.15.1 with checked-in, reproducible 3D bodies for all 73 fitted components and no geometry change. Zero errors-only DRC violations, zero opens: the clean baseline that B2.17 later restarts from.
Adds the carrier half of a straight-through JST PH-8 link to the protected 2S pack controller on the right edge above microSD. Native DRC exposed 192 errors and 59 opens: the connector bodies fit but the copper did not, so the floorplan was re-applied on a clean baseline as B2.17.
Native routing checkpoint B2 line · compact portrait
Restarts from B2.15.2, the last source with zero DRC errors and zero opens, and re-applies the B2.16 floorplan one interface at a time with native DRC after each increment. Keeps the electrical baseline observable instead of letting a placement script certify its own routing.
Proves that a 10-position side-entry JST GH battery connector fits between the USB 2.0 and microSD interfaces without growing the outline, electrically routed and passing errors-only DRC, ERC and parity checks. No fabrication files generated.
Electrically closed · quoted B2 line · compact portrait
Corrects a coupled mechanical and electrical problem in the CM5 socket stack and the clearance to a nearby inductor, moving to exact 1.5 mm Amphenol sockets. Electrically closed with zero errors and zero opens, then quoted.
Placement fix · vias rejected B2 line · compact portrait
Keeps the B2.20 geometry unchanged and fixes the assembler placement rotation for both CM5 sockets from 0° to 90°, with a fail-closed gate that checks pad geometry, STEP identity and the final placement rows together. The board house then rejected its blind and micro vias.
Replaces the 22 microvias and 14 blind vias that the board house rejected with 36 ordinary plated through-vias. Circuit, placements, outline and population are unchanged; released to main.
Withdrawn · mirrored footprints B2 line · compact portrait
Retunes the Type-C RX2 pair after the through-via reroute. Withdrawn: later SMT review exposed mirrored footprints at five parts, so this tree is historical evidence only and must not be fabricated.
Routing experiment B2 line · compact portraitexperiment
Experimental, immutable fork of B2.23 that evaluates tscircuit's KiCad-to-Circuit-JSON conversion and capacity autorouter on the optional 22-pin DSI/CSI interface.
Design start · not fab-ready B2 line · compact portrait
Starts from the released B2.22 source and is reserved for the protected 2S pack charger, NVDC power path and a regulated 5 V system rail. No charger parts are on the board yet; the release command fails closed until the electrical decisions are complete.
Replaces nine reflected generated land patterns with independently library-loaded stock geometry, preserving pad nets and rerouting the affected copper through the official KiCad IPC API. All engineering checkpoint gates pass.
Widens all 50 unsupported 0.07/0.08 mm segments to 0.10 mm with bounded clearance repairs and moves no component. Native DRC: zero errors, zero warnings, zero opens. Uploaded to the assembler's cart for review.
Shifts an existing RX1 dogleg by 0.07 mm to bring the pair's endpoint-length proxy from 0.14 mm to about 0.003 mm. Track widths, components and vias unchanged. The current head of main.
Development fork from B2.23.3 that replaces the out-of-stock Mini HDMI receptacle with a stocked Hirose 20-pin 0.5 mm FFC connector using the standard DIY-HDMI pin order and a catalogue cable. Only the HDMI connector and its local fanout may change.
Fabrication release · latest B2 line · compact portraitlatest
The routed, release-gated version of the HDMI FFC change with the connector on the top side at the bottom edge and every fitted part on the front. Uses the reversed local pin map that an opposite-contact cable requires, locked in a machine-readable connector contract.